The present invention relates to random access memories (RAMs). More specifically, the invention relates to an efficient read/write method and apparatus for RAMs.
RAM devices have become widely accepted in the semiconductor industry. Furthermore, SOC devices typically include internal RAM for storage of information such as instructions and/or data. Internal memory blocks in an SOC device (e.g., a routing chip) typically occupy substantial chip area of an integrated circuit (IC) chip that contains the SOC device. For example, internal memory blocks may occupy as much as about 70% of the IC chip area of an SOC device. The configuration of internal memory in SOC devices are generally similar to the configuration of memory in individual memory chips.
Each block of RAM includes a number of memory cells. Each memory cell typically stores one bit of information. Typical RAM blocks have capacity to store anywhere from thousands to millions of bits of data. Since vast numbers of memory cells are used to store information in RAM blocks, the size of RAM blocks depends, to large extent, on the size of each memory cell.
A conventional memory cell of a static random access memory (SRAM) is typically made up of six transistors in a 6T configuration. Memory cells in dynamic random access memory (DRAM) blocks typically require less number of transistors per bit. DRAMs typically cost less to produce than other types of memory devices due to their relative simplicity. For example, some DRAM blocks contain memory cells with three transistor (3-T) per bit, while other DRAM blocks contain memory cells with one transistor (1-T) per bit. Therefore, DRAM blocks of SOC devices and DRAM chips are typically smaller than SRAM blocks with similar information storage capacity.
However, DRAM cells need to be refreshed periodically for retaining the stored charge. A typical refresh operation comprises of selecting a (group of) memory cell(s), reading the stored values, and writing the stored values back to the respective cells. A typical write operation involves writing the desired data value to the global bit lines to be written to the respective local sense amplifiers. The respective local sense amplifiers then amplify the written values and make the respective local bit lines go either in the same voltage direction as the originally stored values or the opposite direction of the stored value. In order to be able to drive the local bit line to an opposite value, the global bit lines should be designed in such a way to have higher driving capabilities.
In existing DRAMs, global multiplexing information is delivered to the local sense amplifier to prevent erroneous writing to the respective memory cell. This approach gives rise to complicated local sense amplifiers, less area efficiency, and limited multiplexing depth.
Therefore, there is a need for a RAM structure that takes less area, improves core to periphery efficiency, and achieves a better (constant) aspect ratio.
The present invention, modifies the write operation timing to achieve analog global multiplexing with no impact on local sense amplifier area and design complexity. The present invention describes a method and system by which analog multiplexing is used at a global level in hierarchical memories such as Read Only Memories (RAMs) used in system-on-chip (SOC). The advantage of using analog multiplexing at the global level is to reduce area and improve core to periphery efficiency. A further advantage is achieving a better (constant) aspect ratio for wide spectrum memory configurations.
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers)
In one aspect, the present invention is a RAM with analog multiplex sensing means comprising an odd block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective odd bit line; an even block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective even bit line; a plurality of local sense amplifiers positioned between the odd block of data cells and the even block of data cells, each local sense amplifier of the plurality of local sense amplifiers is shared by a respective odd bit line, a respective even bit line, and a respective global bit line; a global sense amplifier electrically coupled to a subset of the plurality of local sense amplifiers by a set of respective global bit lines and having a higher signal driving capability than each of the plurality of local sense amplifiers, wherein one of the set of respective global bit lines is selected for superimposing a signal development on a respective local bit line to be sensed by a respective local sense amplifier and wherein, other global bit lines in the set of respective global bit lines are decoupled from the respective local sense amplifiers.
In another aspect, the present invention is a RAM having a plurality of local bit lines and a plurality of global bit lines comprising means for coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines; means for selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines for a write operation; and means for coupling non-selected global bit lines to a vdd signal.